K4D263238F

K4D263238F 128M DDR SDRAM 128Mbit DDR SDRAM 1M x 32Bit x 4 Banks Double Data Rate Synchronous DRAM with Bi-directional Data Strobe and DLL Revision 1.1 May 2003 - 1 - Rev 1.1 (May 2003) K4D263238F Revision History Revision 1.1 (May 30, 2003) Added Lead Free package part number in the datasheet. 128M DDR SDRAM Revision 1.0 (April 29, 2003) Define DC spec. Revision 0.0 (January 20, 2003)- Target spec Define target spec. - 2 - Rev 1.1 (May 2003) K4D263238F 128M DDR SDRAM 1M x 32Bit x 4 Banks Double Data Rate Synchronous DRAM with Bi-directional Data Strobe and DLL FEATURES 2.5V ± 5% power supply for device operation 2.5V ± 5% power supply for I/O interface SSTL_2 compatible inputs/outputs 4 banks operation MRS cycle with address key programs -. Read latency 3 (clock) -. Burst length (2, 4, 8 and Full page) -. Burst type (sequential & interleave) Full page burst length for sequential burst type only Start address of the full page burst should be even All inputs except data & DM are sampled at the positive going edge of the system clock Differential clock input No Write Interrupted by Read function Data I/O transactions on both edges of Data strobe DLL aligns DQ and DQS transitions with Clock transition Edge aligned data & data strobe output Center aligned data & data strobe input DM for write masking only Auto & Self refresh 32ms refresh period (4K cycle) 100pin TQFP package Maximum clock frequency up to 250MHz Maximum d...