K4D263238D

K4D263238D 128M DDR SDRAM 128Mbit DDR SDRAM 1M x 32Bit x 4 Banks Double Data Rate Synchronous DRAM with Bi-directional Data Strobe and DLL Revision 1.3 July 2002 - 1 - Rev. 1.3 (Jul. 2002) K4D263238D Revision History Revision 1.3 (July 18, 2002) Changed power dissipation from 2.0W to 1.8W 128M DDR SDRAM Revision 1.2 (June 17, 2002) Removed K4D263238D-QC55 from the spec. 183/166MHz were supported in K4D263238D-QC50. Revision 1.1 (May 24, 2002) Removed K4D263238D-QC45/60 from the spec Revision 1.0 (May 20, 2002) Define DC spec. Revision 0.0 (April 23, 2002)- Target spec Define target spec. - 2 - Rev. 1.3 (Jul. 2002) K4D263238D 128M DDR SDRAM 1M x 32Bit x 4 Banks Double Data Rate Synchronous DRAM with Bi-directional Data Strobe and DLL FEATURES 2.5V ± 5% power supply SSTL_2 compatible inputs/outputs 4 banks operation MRS cycle with address key programs -. Read latency 3,4 (clock) -. Burst length (2, 4, 8 and Full page) -. Burst type (sequential & interleave) Full page burst length for sequential burst type only Start address of the full page burst should be even All inputs except data & DM are sampled at the positive going edge of the system clock Differential clock input No Write Interrupted by Read function Data I/O transactions on both edges of Data strobe DLL aligns DQ and DQS transitions with Clock transition Edge aligned data & data strobe output Center aligned data & data strobe input DM for write masking only Auto...