IW4012B

TECHNICAL DATA IW4012B Dual 4-Input NAND Gate High-Voltage Silicon-Gate CMOS The IW4012B NAND gates provide the system designer with direct emplementation of the NAND function. Operating Voltage Range: 3.0 to 18 V Maximum input current of 1 µA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C Noise margin (over full package temperature range): 1.0 V min @ 5.0 V supply 2.0 V min @ 10.0 V supply 2.5 V min @ 15.0 V supply ORDERING INFORMATION IW4012BN Plastic IW4012BD SOIC TA = -55° to 125° C for all packages LOGIC DIAGRAM PIN ASSIGNMENT NC = NO CONNECTION PINS 6, 8 = NO CONNECTION PIN 14 =VCC PIN 7 = GND A L X X X H FUNCTION TABLE Inputs B X L X X H C X X L X H D X X X L H Output Y H H H H L w w w .d h s a t a ee . u t4 m o c X = don’t care 1 www.DataSheet4U.com IW4012B MAXIMUM RATINGS* Symbol VCC VIN VOUT IIN PD PD Tstg TL * Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) DC Output Voltage (Referenced to GND) DC Input Current, per Pin Power Dissipation in Still Air, Plastic DIP+ SOIC Package+ Power Dissipation per Output Transistor Storage Temperature Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package) Value -0.5 to +20 -0.5 to VCC +0.5 -0.5 to VCC +0.5 ±10 750 500 100 -65 to +150 260 Unit V V V mA mW mW °C °C Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions...