16Mx32 512Mb DDR2 DRAM
IS43/46DR32160C
16Mx32 512Mb DDR2 DRAM
FEATURES • Vdd = 1.8V ±0.1V, Vddq = 1.8V ±0.1V
• JEDEC standard 1.8V I/O (S...
Description
IS43/46DR32160C
16Mx32 512Mb DDR2 DRAM
FEATURES Vdd = 1.8V ±0.1V, Vddq = 1.8V ±0.1V
JEDEC standard 1.8V I/O (SSTL_18-compatible)
Double data rate interface: two data transfers per clock cycle
Differential data strobe (DQS, DQS)
4-bit prefetch architecture
On chip DLL to align DQ and DQS transitions with CK
4 internal banks for concurrent operation
Programmable CAS latency (CL) 3, 4, 5, and 6 supported
Posted CAS and programmable additive latency (AL) 0, 1, 2, 3, 4, and 5 supported
WRITE latency = READ latency - 1 tCK
Programmable burst lengths: 4 or 8
Adjustable data-output drive strength, full and reduced strength options
On-die termination (ODT)
OPTIONS Configuration:
16M x 32 (IS43/46DR32160C - 8K refresh)
Package: x32: 126-ball WBGA
Timing – Cycle time 2.5ns @CL=6, DDR2-800E 3.0ns @CL=5, DDR2-667D 3.75ns @CL=4, DDR2-533C 5.0ns @CL=3, DDR2-400B
Temperature Range: Commercial (0°C ≤ Tc ≤ 85°C; 0°C ≤ Ta ≤ 70°C) Industrial (–40°C ≤ Tc ≤ 95°C; –40°C ≤ Ta ≤ 85°C) Automotive, A1 (–40°C ≤ Tc ≤ 95°C; –40°C ≤ Ta ≤ 85°C) Automotive, A2 (–40°C ≤ Tc ≤ 105°C; –40°C ≤ Ta ≤ 105°C) Tc = Case Temp, Ta = Ambient Temp
NOVEMBER 2013
DESCRIPTION
ISSI's 512Mb DDR2 SDRAM uses a double-data-rate architecture to achieve high-speed operation. The double-data rate architecture is essentially a 4n-prefetch architecture, with an interface designed to transfer two data words per clock cycle at the I/O balls.
The 512Mb DDR2 SDRAM is provided in ...
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