IS42S16400

IS42S16400 om c . 1 Meg Bits x 16 UBits x 4 Banks (64-MBIT) FINAL PRODUCTION 4 t SYNCHRONOUS DYNAMIC RAM MAY 2001 e e FEATURES h OVERVIEW S ISSI's 64Mb Synchronous DRAM IS42S16400 is organized Clock frequency: 166, 133, 100 MHz a as 1,048,576 bits x 16-bit x 4-bank for improved t Fully synchronous; all signals referenced to a a performance. The synchronous DRAMs achieve high-speed positive D clock edge data transfer using pipeline architecture. All inputs and . outputs signals refer to the rising edge of the clock input. Internal bank for hiding row access/precharge w w 3.3V power supply w Single LVTTL interface PIN CONFIGURATIONS Programmable burst length – (1, 2, 4, 8, full page) Programmable burst sequence: Sequential/Interleave Self refresh modes ISSI ® 4096 refresh cycles every 64 ms Random column address every clock cycle Programmable CAS latency (2, 3 clocks) Burst read/write and burst read/single write operations capability Burst termination by burst stop and precharge command Byte controlled by LDQM and UDQM Industrial temperature availability Package: 400-mil 54-pin TSOP II PIN DESCRIPTIONS A0-A11 BA0, BA1 I/O0 to I/O15 CLK CKE CS RAS CAS m o .c U 4 t e e h S a t a .D w w w 54-Pin TSOP (Type II) VCC I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 1 2 3 4 5 6 7 8 9 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 VCCQ GNDQ VCCQ 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 GNDQ VCC WE LDQM CAS RAS ...