TECHNICAL DATA
Octal 3-State Noninverting Transparent Latch
High-Performance Silicon-Gate CMOS
The IN74AC573 is identic...
TECHNICAL DATA
Octal 3-State Noninverting Transparent Latch
High-Performance Silicon-Gate
CMOS
The IN74AC573 is identical in pinout to the LS/ALS573, HC/HCT573. The device inputs are compatible with standard
CMOS outputs; with pullup resistors, they are compatible with LS/ALS outputs. These latches appear transparent to data (i.e., the outputs change asynchronously) when Latch Enable is high. When Latch Enable goes low, data meeting the setup and hold time becomes latched. Outputs Directly Interface to
CMOS, NMOS, and TTL Operating
Voltage Range: 2.0 to 6.0 V Low Input Current: 1.0 µA; 0.1 µA @ 25°C High Noise Immunity Characteristic of
CMOS Devices Outputs Source/Sink 24 mA
IN74AC573
ORDERING INFORMATION IN74AC573N Plastic IN74AC573DW SOIC TA = -40° to 85° C for all packages
PIN ASSIGNMENT LOGIC DIAGRAM
FUNCTION TABLE
PIN 20=VCC PIN 10 = GND Inputs Output Enable L L L H Latch Enable H H L X D H L X X Output Q H L no change Z
w
w
w
.d
h s a t a
ee
. u t4
m o c
X = don’t care Z = high impedance
1
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IN74AC573
MAXIMUM RATINGS*
Symbol VCC VIN VOUT IIN IOUT ICC PD Tstg TL
*
Parameter DC Supply
Voltage (Referenced to GND) DC Input
Voltage (Referenced to GND) DC Output
Voltage (Referenced to GND) DC Input Current, per Pin DC Output Sink/Source Current, per Pin DC Supply Current, VCC and GND Pins Power Dissipation in Still Air, Plastic DIP+ SOIC Package+ Storage Temperature Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or ...
