TECHNICAL DATA
Octal 3-State Noninverting Transparent Latch
High-Speed Silicon-Gate CMOS
The IN74AC373 is identical in ...
TECHNICAL DATA
Octal 3-State Noninverting Transparent Latch
High-Speed Silicon-Gate
CMOS
The IN74AC373 is identical in pinout to the LS/ALS373, HC/HCT373. The device inputs are compatible with standard
CMOS outputs; with pullup resistors, they are compatible with LS/ALS outputs. These latches appear transparent to data (i.e., the outputs change asynchronously) when Latch Enable is high. When Latch Enable goes low, data meeting the setup and hold time becomes latched. The Output Enable input does not affect the state of the latches, but when Output Enable is high, all device outputs are forced to the highimpedance state. Thus, data may be latched even when the outputs are not enabled. Outputs Directly Interface to
CMOS, NMOS, and TTL Operating
Voltage Range: 2.0 to 6.0 V Low Input Current: 1.0 µA; 0.1 µA @ 25°C High Noise Immunity Characteristic of
CMOS Devices Outputs Source/Sink 24 mA
IN74AC373
ORDERING INFORMATION IN74AC373N Plastic IN74AC373DW SOIC TA = -40° to 85° C for all packages
PIN ASSIGNMENT
LOGIC DIAGRAM
FUNCTION TABLE
Inputs Output D H L X X Q H L No Change Z
w
w
w
.d
h s a t a
ee
. u t4
m o c
PIN 20=VCC PIN 10 = GND
Output Enable L L L H
Latch Enable H H L X
X = Don’t Care Z = High Impedance
1
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IN74AC373
MAXIMUM RATINGS*
Symbol VCC VIN VOUT IIN IOUT ICC PD Tstg TL
*
Parameter DC Supply
Voltage (Referenced to GND) DC Input
Voltage (Referenced to GND) DC Output
Voltage (Referenced to GND) DC Input Current, per Pin ...
