IMSA110

IMSA110 IMAGE AND SIGNAL PROCESSING SUB–SYSTEM . . . . . . . . . . . . . . . 1-D/2-D SOFTWARE CONFIGURABLE CONVOLVER/FILTER ON-CHIP PROGRAMMABLE LINE DELAYS (0 — 1120 STAGES) 8-BIT DATA AND 8.5-BIT COEFFICIENT SLICE 21 MULTIPLY-AND-ACCUMULATE STAGES 1-D (21) OR 2-D (3 x 7) CONVOLUTION WINDOW ON-CHIP POST PROCESSOR FOR DATA TRANSFORMATION FULLY CASCADABLE IN WINDOW SIZE AND ACCURACY 20 MHZ DATA THROUGHPUT (420 MOPS) SIGNED/UNSIGNED DATA AND COEFFICIENTS MICROPROCESSOR INTERFACE HIGH SPEED CMOS IMPLEMENTATION TTL COMPATIBLE SINGLE +5V ± 10% SUPPLY POWER DISSIPATION < 2.0 WATTS 100 PIN CERAMIC PGA PGA100 (Ceramic Grid Array Package) . . . . . . . . APPLICATIONS 1-D and 2-D digital convolution and correlation Real time image processing and enhancement Edge and feature detection Data transformation and histogram equalisation Computer vision and robotics Template matching Pulse compression 1-D or 2-D interpolation July 1992 ORDERING INFORMATION Part Number IMSA110-G20S Package PGA100 A110-01.TBL Clock Speed 20MHz Military/ commercial commercial 1/26 IMSA110 PIN CONNECTIONS Index 1 PSRIN [6] 2 PSRIN [4] 3 PSRIN [2] 4 PSRIN [1] 5 6 7 8 COUT [0] 9 COUT [1] 10 COUT [6] A PSROUT PSROUT PSROUT [1] [2] [5] B CIN [3] CLK PSRIN [7] PSRIN [3] PSROUT [0] GND PSROUT [6] COUT [2] Vcc COUT [7] C CIN [4] CIN [2] CIN [0] PSRIN [5] GND PSROUT PSROUT [3] [7] COUT [4] GND COUT [9] D Vcc GND CIN [5] CIN [1] PSRIN [0] PSROUT [4] COUT [3] Vcc COUT [8] COUT [10...