IDTCSP2510C

IDTCSP2510C 3.3V PHASE-LOCK LOOP CLOCK DRIVER 0ºC TO 85ºC TEMPERATURE RANGE 3.3V PHASE-LOCK LOOP CLOCK DRIVER ZERO DELAY BUFFER FEATURES: Phase-Lock Loop Clock Distribution for Synchronous DRAM Applications Distributes one clock input to one bank of ten outputs Output enable bank control External feedback (FBIN) pin is used to synchronize the outputs to the clock input signal No external RC network required for PLL loop stability Operates at 3.3V VDD tpd Phase Error at 133MHz: < ±150ps Jitter (peak-to-peak) at 133MHz: < ±75ps @ 133MHz Spread Spectrum Compatible Operating frequency 25MHz to 140MHz Available in 24-Pin TSSOP package IDTCSP2510C APPLICATIONS: SDRAM Modules PC Motherboards Workstations The CSP2510C is a high performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a PLL to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It is specifically designed for use with synchronous DRAMs. The CSP2510C operates at 3.3V. One bank of ten outputs provide low-skew, low-jitter copies of CLK. Output signal duty cycles are adjusted to 50 percent, independent of the duty cycle at CLK. The outputs can be enabled or disabled via the control G input. When the G input is high, the outputs switch in phase and frequency with CLK; when the G input is low, the outputs are disabled to the logic-low state. Unlike many products containing PLLs, the CSP2510C does not require externa...