IDT74SSTU32866B

www.DataSheet4U.com IDT74SSTUB32866B 1.8V CONFIGURABLE REGISTERED BUFFER WITH PARITY COMMERCIAL TEMPERATURE RANGE 1.8V CONFIGURABLE BUFFER WITH PARITY IDT74SSTUB32866B ADVANCE INFORMATION FEATURES: 1.8V Operation SSTL_18 style clock and data inputs Differential CLK input Configurable as 25-bit 1:1 or 14-bit 1:2 registered buffer Control inputs compatible with LVCMOS levels Flow-through architecture for optimum PCB design Latch-up performance exceeds 100mA ESD >2000V per MIL-STD-883, Method 3015; >200V using machine model (C = 200pF, R = 0) Checks parity on data inputs Maximum operating frequency: 410MHz Optimized for DDR2 - 400 / 533 / 667 / 800 (PC2 - 3200 / 4300 / 5300 / 6400) JEDEC R/C E, F, G, H, and J Available in 96-pin LFBGA package APPLICATIONS: Along with CSPUA877 DDR2 PLL, provides complete solution for DDR2 DIMMs DESCRIPTION: This 25-bit 1:1 / 14-bit 1:2 configurable registered buffer is designed for 1.7V to 1.9V VDD operation. In the 1:1 pinout configuration, only one device per DIMM is requred to drive nine SDRAM loads. In the 1:2 pinout configuration, two devices per DIMM are required to drive eighteen SDRAM loads. All inputs are SSTL_18, except reset (RESET) and control (Cn) inputs, which are LVCMOS. All outputs are edge-controlled circuits optimized for unterminated DIMM loads, and meet SSTL_18 specifications, except the open-drain error (QERR) output. The SSTUB32866B operates from a differential clock (CLK and CLK). Data ar...