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IDT72V3680 Datasheet

Part Number IDT72V3680
Manufacturers Integrated Device Tech
Logo Integrated Device Tech
Description CMOS FIFO memories
Datasheet IDT72V3680 DatasheetIDT72V3680 Datasheet (PDF)

3.3 VOLT HIGH-DENSITY SUPERSYNC™ II 36-BIT FIFO 1,024 x 36, 2,048 x 36 4,096 x 36, 8,192 x 36 16,384 x 36, 32,768 x 36 65,536 x36, 131,072 x 36 IDT72V3640, IDT72V3650 IDT72V3660, IDT72V3670 IDT72V3680, IDT72V3690 IDT72V36100, IDT72V36110 • • • • • • • • • • • • • • • FEATURES: • • • • • • Choose among the following memory organizations:Commercial IDT72V3640  1,024 x 36 IDT72V3650  2,048 x 36 IDT72V3660  4,096 x 36 IDT72V3670  8,192 x 36 IDT72V3680  16,384 x 36 IDT72V3690  32,768 x 36.

  IDT72V3680   IDT72V3680






Part Number IDT72V3680
Manufacturers Renesas
Logo Renesas
Description 3.3V HIGH-DENSITY 36-BIT FIFO
Datasheet IDT72V3680 DatasheetIDT72V3680 Datasheet (PDF)

3.3V HIGH-DENSITY SUPERSYNC™ II 36-BIT FIFO 1,024 x 36, 2,048 x 36 IDT72V3640, IDT72V3650 4,096 x 36, 8,192 x 36 IDT72V3660, IDT72V3670 16,384 x 36, 32,768 x 36 IDT72V3680, IDT72V3690 LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018 FEATURES: • Choose among the following memory organizations:Commercial IDT72V3640 ⎯ 1,024 x 36 IDT72V3650 ⎯ 2,048 x 36 IDT72V3660 ⎯ 4,096 x 36 IDT72V3670 ⎯ 8,192 x 36 IDT72V3680 ⎯ 16,384 x 36 IDT72V3690 ⎯ 32,768 x 36 • Up to 166 MHz.

  IDT72V3680   IDT72V3680







CMOS FIFO memories

3.3 VOLT HIGH-DENSITY SUPERSYNC™ II 36-BIT FIFO 1,024 x 36, 2,048 x 36 4,096 x 36, 8,192 x 36 16,384 x 36, 32,768 x 36 65,536 x36, 131,072 x 36 IDT72V3640, IDT72V3650 IDT72V3660, IDT72V3670 IDT72V3680, IDT72V3690 IDT72V36100, IDT72V36110 • • • • • • • • • • • • • • • FEATURES: • • • • • • Choose among the following memory organizations:Commercial IDT72V3640  1,024 x 36 IDT72V3650  2,048 x 36 IDT72V3660  4,096 x 36 IDT72V3670  8,192 x 36 IDT72V3680  16,384 x 36 IDT72V3690  32,768 x 36 IDT72V36100  65,536 x 36 IDT72V36110  131,072 x 36 133 MHz operation (7.5 ns read/write cycle time) User selectable input and output port bus-sizing - x36 in to x36 out - x36 in to x18 out - x36 in to x9 out - x18 in to x36 out - x9 in to x36 out Big-Endian/Little-Endian user selectable byte representation 5V input tolerant Fixed, low first word latency Zero latency retransmit Auto power down minimizes standby power consumption Master Reset clears entire FIFO Partial Reset clears data, but retains programmable settings Empty, Full and Half-Full flags signal FIFO status Programmable Almost-Empty and Almost-Full flags, each flag can default to one of eight preselected offsets Selectable synchronous/asynchronous timing modes for AlmostEmpty and Almost-Full flags Program programmable flags by either serial or parallel means Select IDT Standard timing (using EF and FF flags) or First Word Fall Through timing (using OR and IR flags) Output enable puts data outputs into high impedance sta.


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