3.3 VOLT CMOS SyncFIFOTM WITH
BUS-MATCHING
256 x 36
IDT72V3623
1,024 x 36
IDT72V3643
LEAD FINISH (SnPb) ARE IN EOL...
3.3 VOLT
CMOS SyncFIFOTM WITH
BUS-MATCHING
256 x 36
IDT72V3623
1,024 x 36
IDT72V3643
LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018
FEATURES:
Memory storage capacity: IDT72V3623–256 x 36 IDT72V3643–1,024 x 36
Clock frequencies up to 100 MHz (6.5 ns access time) Clocked FIFO buffering data from Port A to Port B IDT Standard timing (using EF and FF) or First Word Fall
Through Timing (using OR and IR flag functions) Programmable Almost-Empty and Almost-Full flags; each has
three default offsets (8, 16 and 64) Serial or parallel programming of partial flags Port B bus sizing of 36 bits (long word), 18 bits (word) and 9 bits
(byte) Big- or Little-Endian format for word and byte bus sizes
Reset clears data and configures FIFO, Partial Reset clears data but retains configuration settings
Mailbox bypass registers for each FIFO Free-running CLKA and CLKB may be asynchronous or
coincident (simultaneous reading and writing of data on a single clock edge is permitted) Easily expandable in width and depth Auto power down minimizes power dissipation Available in a space-saving 128-pin Thin Quad Flatpack (TQFP) Pin and functionally compatible versions of the 5V operating IDT723623/723643 Industrial temperature range (–40°C to +85°C) is available Green parts available, see ordering information
FUNCTIONAL BLOCK DIAGRAM
MBF1
CLKA CSA
W/RA ENA MBA
RS1 RS2 PRS
Port-A Control Logic
FIFO1 Mail1, Mail2, Reset Logic
36
Mai...