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IDT72V215

Integrated Device Technology

FIFO memories

3.3 VOLT CMOS SyncFIFOTM 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18, and 4,096 x 18 IDT72V205, IDT72V215, IDT72V225, ID...



IDT72V215

Integrated Device Technology


Octopart Stock #: O-248552

Findchips Stock #: 248552-F

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Description
3.3 VOLT CMOS SyncFIFOTM 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18, and 4,096 x 18 IDT72V205, IDT72V215, IDT72V225, IDT72V235, IDT72V245 FEATURES: • • • • • • • • • • • • • • • • • DESCRIPTION: The IDT72V205/72V215/72V225/72V235/72V245 are functionally compatible versions of the IDT72205LB/72215LB/72225LB/72235LB/72245LB, designed to run off a
More View 3.3V supply for exceptionally low power consumption. These devices are very high-speed, low-power First-In, First-Out (FIFO) memories with clocked read and write controls. These FIFOs are applicable for a wide variety of data buffering needs, such as optical disk controllers, Local Area Networks (LANs), and interprocessor communication. These FIFOs have 18-bit input and output ports. The input port is controlled by a free-running clock (WCLK), and an input enable pin (WEN). Data is read into the synchronous FIFO on every clock when WEN is asserted. The output port is controlled by another clock pin (RCLK) and another enable pin (REN). The Read Clock(RCLK) can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual-clock operation. An Output Enable pin (OE) is provided on the read port for three-state control of the output. The synchronous FIFOs have two fixed flags, Empty Flag/Output Ready (EF/OR) and Full Flag/Input Ready (FF/IR), and two programmable flags, Almost-Empty (PAE) and Almost-Full (PAF). The offset loading of the program- 256 x 18-bit organization array (IDT72V205) 512 x 18-bit organization array (IDT72V215) 1,024 x 18-bit organization array (IDT72V225) 2,048 x 18-bit organization array (IDT72V235) 4,096 x 18-bit organization array (IDT72V245) 10 ns read/write cycle time 5V input tolerant IDT Standard or First Word Fall Through timing Single or double register-buffered Empty and Full flags Easily expandable in depth and width Asynchronous or coincident Read and Write Clocks Asynchronous or synchronous programmable Almost-Empty and Almost-Full flags with default settings Half-Full flag capability Output enable puts output data bus in high-impedanc state High-performance submicron CMOS technology Available in a 64-lead thin quad flatpack (TQFP/STQFP) Industrial temperature range (–40°C to +85°C) is available FUNCTIONAL BLOCK DIAGRAM WEN WCLK D0-D17 LD INPUT REGISTER OFFSET REGISTER FF/IR PAF EF/OR PAE HF/(WXO) WRITE CONTROL LOGIC FLAG LOGIC RAM ARRAY 256 x 18, 512 x 18 1,024 x 18, 2,048 x 18 4,096 x 18 WRITE POINTER FL WXI (HF)/WXO RXI RXO RS READ POINTER READ CONTROL LOGIC EXPANSION LOGIC OUTPUT REGISTER RESET LOGIC OE Q0-Q17 RCLK REN 4294 drw 01 IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. SyncFIFO is a trademark of Integrated Device Technology, Inc. COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES 1 ©2002 Integrated Device Tech






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