CMOS PARALLEL-TO-SERIAL FIFO 256 x 16, 512 x 16, 1024 x 16
Integrated Device Technology, Inc.
IDT72105 IDT72115 IDT7212...
CMOS PARALLEL-TO-SERIAL FIFO 256 x 16, 512 x 16, 1024 x 16
Integrated Device Technology, Inc.
IDT72105 IDT72115 IDT72125
FEATURES:
25ns parallel port access time, 35ns cycle time 45MHz serial output shift rate Wide x16 organization offering easy expansion Low power consumption (50mA typical) Least/Most Significant Bit first read selected by asserting the FL/DIR pin Four memory status flags: Empty, Full, Half-Full, and Almost-Empty/Almost-Full Dual-Port zero fall-through architecture Available in 28-pin 300 mil plastic DIP and 28-pin SOIC Industrial temperature range (-40oC to +85oC) is available, tested to military electrical specifications
DESCRIPTION:
The IDT72105/72115/72125s are very high-speed, lowpower,dedicated, parallel-to-serial FIFOs. These FIFOs possess a 16-bit parallel input port and a serial output port with 256, 512 and 1K word depths, respectively. The ability to buffer wide word widths (x16) make these FIFOs ideal for laser printers, FAX machines, local area networks (LANs), video storage and disk/tape controller applications. Expansion in width and depth can be achieved using multiple chips. IDT’s unique serial expansion logic makes this possible using a minimum of pins. The unique serial output port is driven by one data pin (SO) and one clock pin (SOCP). The Least Significant or Most Significant Bit can be read first by programming the DIR pin after a reset. Monitoring the FIFO is eased by the availability of four status flags: Empty, ...
