IDT71V546

128K x 36, 3.3V Synchronous IDT71V546 SRAM with ZBT™ Feature, Burst Counter and Pipelined Outputs Features 128K x 36 memory configuration, pipelined outputs Supports high performance system speed - 133 MHz (4.2 ns Clock-to-Data Access) ZBTTM Feature - No dead cycles between write and read cycles Internally synchronized registered outputs eliminate the need to control OE Single R/W (READ/WRITE) control pin Positive clock-edge triggered address, data, and control signal registers for fully pipelined applications 4-word burst capability (interleaved or linear) Individual byte write (BW1 - BW4) control (May tie active) Three chip enables for simple depth expansion Single 3.3V power supply (±5%) Packaged in a JEDEC standard 100-pin TQFP package clock cycle, and two cycles later its associated data cycle occurs, be it read or write. The IDT71V546 contains data I/O, address and control signal registers. Output enable is the only asynchronous signal and can be used to disable the outputs at any given time. A Clock Enable (CEN) pin allows operation of the IDT71V546 to be suspended as long as necessary. All synchronous inputs are ignored when CEN is high and the internal device registers will hold their previous values. There are three chip enable pins (CE1, CE2, CE2) that allow the user to deselect the device when desired. If any one of these three is not active when ADV/LD is low, no new memory operation can be initiated and any burst that was in progress is stopped. However, any pen...