IDT7028L

HIGH-SPEED 64K x 16 DUAL-PORT STATIC RAM Features x x x IDT7028L x x x True Dual-Ported memory cells which allow simultaneous reads of the same memory location High-speed access – Commercial: 15/20ns (max.) Low-power operation – IDT7028L Active: 1W (typ.) Standby: 1mW (typ.) Dual chip enables allow for depth expansion without external logic IDT7028 easily expands data bus width to 32 bits or more using the Master/Slave select when cascading more than one device x x x x x x x x M/S = VIH for BUSY output flag on Master, M/S = VIL for BUSY input on Slave Interrupt Flag On-chip port arbitration logic Full on-chip hardware support of semaphore signaling between ports Fully asynchronous operation from either port Separate upper-byte and lower-byte controls for multiplexed bus and bus matching compatibility TTL-compatible, single 5V (±10%) power supply Available in a 100-pin TQFP Industrial temperature range (–40°C to +85°C) is available for selected speeds Functional Block Diagram R/WL UBL CE0L CE1L OEL LBL R/WR UBR CE0R CE1R OER LBR I/O 8-15L I/O 0-7L BUSYL (1,2) A15L A0L 64Kx16 MEMORY ARRAY 7028 16 16 I/O8-15R I/O Control I/O Control I/O0-7R BUSYR A15R A0R (1,2) Address Decoder Address Decoder CE0L CE1L OEL R/WL SEML ARBITRATION INTERRUPT SEMAPHORE LOGIC CE0R CE1R OER R/WR SEMR (2) INTR 4836 drw 01 M/S NOTES: 1. BUSY is an input as a Slave (M/S = VIL) and an output when it is a Master (M/S = VIH). 2. BUSY and INT are non-tri-state totem-pole outputs (push-pull)....