ICS93716YG-T

Integrated Circuit Systems, Inc. ICS93716 Low Cost DDR Phase Lock Loop Clock Driver Recommended Application: DDR Clock Driver Product Description/Features: Low skew, low jitter PLL clock driver I2C for functional and output control Feedback pins for input to output synchronization Spread Spectrum tolerant inputs Switching Characteristics: PEAK - PEAK jitter (66MHz): <120ps PEAK - PEAK jitter (>100MHz): <75ps CYCLE - CYCLE jitter (>100MHz):<65ps OUTPUT - OUTPUT skew: <100ps Output Rise and Fall Time: 650ps - 950ps Pin Configuration CLKC0 CLKT0 VDD CLKT1 CLKC1 GND SCLK CLK_INT CLK_INC VDDA GND VDD CLKT2 CLKC2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 GND CLKC5 CLKT5 CLKC4 CLKT4 VDD SDATA FBINC FBINT FB_OUTT FB_OUTC CLKT3 CLKC3 GND 28-Pin SSOP and TSSOP Functionality INPUTS AVDD CLK_INT 2.5V (nom) 2.5V (nom) 2.5V (nom) L H <20MHz L H H L CLK_INC CLKT CLKC H L L H Z L H H L Z H L OUTPUTS FB_OUTT FB_OUTC L H Z L H H L Z H L PLL State on on off Bypassed/off Bypassed/off Block Diagram GND GND FB_OUTT FB_OUTC SCLK SDATA Control Logic CLKT0 CLKC0 CLKT1 CLKC1 CLKT2 CLKC2 FB_INT FB_INC CLK_INC CLK_INT CLKT3 CLKC3 PLL CLKT4 CLKC4 CLKT5 CLKC5 0420E—04/01/03 ICS93716 ICS93716 Pin Descriptions PIN NUMBER 6, 11, 15, 28 PIN NAME GND TYPE PWR OUT OUT PWR Ground "Complementar y" clocks of differential pair outputs. "Tr ue" Clock of differential pair outputs. Power supply 2.5V DESCRIPTION 27, 25, 16, 14, 5, 1 CLKC(5:0) 26, 24,...