ICS9250-32

Integrated Circuit Systems, Inc. ICS9250-32 Frequency Generator & Integrated Buffers for PII/III™ Recommended Application: Timna Style Chipset Output Features: 3 - CPUs @ 2.5V 8 - PCI @ 3.3V 2 - IOAPIC @ 2.5V 1 - MREF @ 2.5V, DRCG memory reference clock 9 - SDRAM @ 3.3V including one free running 1 - 2V48M @ 2.5V fixed (DOT) 1 - 3V48M @ 3.3V fixed (USB) 2 - REF @ 3.3V, 14.318MHz. Features: Support power management: CPU, PCI, SDRAM stop from I2C programming. Spread spectrum for EMI control (0 to -0.5%) Uses external 14.318MHz crystal Key Specifications: CPU Output Jitter (Cyc-Cyc): <175ps IOAPIC Output Jitter (Cyc-Cyc): <500ps MREF Output Jitter (Cyc-Cyc): <250ps 2V48M Output Jitter (Cyc-Cyc): <250ps 3V48M Output Jitter (Cyc-Cyc): <500ps CPU - CPU: < 175ps SDRAM - SDRAM < 250ps PCI - PCI: < 500ps IOAPIC - IOAPIC: < 250ps BUFFER_IN to SDRAM prop delay: 5.5 to 7.5ns Pin Configuration 2V48M 3V48M VDD48 GND48 X1 X2 GND *(CPU2_EN#)REF0 REF1 VDD PCICLK0 PCICLK1 GNDPCI VDDPCI PCICLK2 PCICLK3 PCICLK4 PCICLK5 VDDPCI GNDPCI PCICLK6 PCICLK7 SCLK VDDA GNDA SDATA BUF_IN *FS0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 VDDLIOAPIC IOAPIC0 IOAPIC1 GNDLIOAPIC VDDLCPU CPUCLK0 CPUCLK1 VDDLCPU GNDLCPU CPUCLK2 MREF66 VDD SDRAM_F SDRAM0 VDDSDR GNDSDR SDRAM1 SDRAM2 SDRAM3 GNDSDR VDDSDR SDRAM4 SDRAM5 VDDSDR GNDSDR SDRAM6 SDRAM7 FS1* 56-Pin 30...