PRELIMINARY
Integrated Circuit Systems, Inc.
ICS8344
LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER
FEATURES
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PRELIMINARY
Integrated Circuit Systems, Inc.
ICS8344
LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-LV
CMOS FANOUT BUFFER
FEATURES
24 LV
CMOS outputs, 7Ω typical output impedance Output frequency up to 167MHz 275ps output skew, 600ps part to part skew Translates any differential input signal (PECL, HSTL, LVDS) to LV
CMOS without external bias networks Translates any single-ended input signal to LV
CMOS with resistor bias on nCLK input Translates and inverts any single-ended input signal to LV
CMOS with resistor bias on CLK input Multiple differential clock input pairs for redundant clock applications LV
CMOS control inputs Multiple output enable pins for disabling unused outputs in reduced fanout applications 3.3V, 2.5V or mixed 3.3V, 2.5V operating supply modes 48 lead low-profile QFP(LQFP), 7mm x 7mm x 1.4mm package body, 0.5mm package lead pitch 0°C to 70°C ambient operating temperature Industrial temperature versions available upon request
GENERAL DESCRIPTION
The ICS8344 is a low
voltage, low skew fanout buffer and a member of the HiPerClockS™ HiPerClockS™ family of High Performance Clock Solutions from ICS. The ICS8344 is designed to translate any differential signal levels to LV
CMOS levels. The low impedance LV
CMOS outputs are designed to drive 50Ω series or parallel terminated transmission lines. The effective fanout can be increased to 48 by utilizing the ability of the outputs to drive two series terminated lines. Redundant clock www.DataSheet4U.com applicat...