HYI25D256800C

March 2007 HYB25D256[40/80/16]0CE(L) HYB25D256[40/80/16]0C[T/C/F] HYI25D256[80/16]0C[C/E/F/T] www.DataSheet4U.com 256-Mbit Double-Data-Rate SDRAM DDR SDRAM RoHS Compliant or Lead-Containing Internet Data Sheet Rev. 2.3 Internet Data Sheet HY[B/I]25D256[16/40/80]0C[E/C/F/T](L) 256 Mbit Double-Data-Rate SDRAM HYB25D256[40/80/16]0CE(L), HYB25D256[40/80/16]0C[T/C/F], HYI25D256[80/16]0C[C/E/F/T] Revision History: 2007-03, Rev. 2.3 Page All 17 www.DataSheet4U.com 72 85, 86 Subjects (major changes since last revision) Adapted internet edition Corrected table 7 mode register definition Changed the 1.1 mA to 1.5 mA for low power Changed the ball size from 0.460 mm to 0.450 mm Previous Revision: 2007-01, Rev. 2.2 We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to: techdoc@qimonda.com qag_techdoc_rev400 / 3.2 QAG / 2006-08-07 03062006-8CCM-VPUW 2 Internet Data Sheet HY[B/I]25D256[16/40/80]0C[E/C/F/T](L) 256 Mbit Double-Data-Rate SDRAM 1 www.DataSheet4U.com Overview Features Auto Precharge option for each burst access Auto Refresh and Self Refresh Modes RAS-lockout supported tRAP = tRCD 7.8 µs Maximum Average Periodic Refresh Interval 2.5 V (SSTL_2 compatible) I/O VDDQ = 2.5 V ± 0.2 V (DDR200, DDR266, DDR333); VDDQ = 2.6 V ± 0.1 V (DDR400) V...