HYB5117400BJ-60

4M × 4-Bit Dynamic RAM 2k & 4k Refresh (Fast Page Mode) Advanced Information 4 194 304 words by 4-bit organization 0 to 70 °C operating temperature Fast Page Mode operation Performance: -50 -60 60 15 30 40 ns ns ns ns HYB 5116400BJ-50/-60 HYB 5117400BJ-50/-60 HYB 3116400BJ/BT-50/-60 HYB 3117400BJ-50/-60 tRAC RAS access time tCAC CAS access time tAA tRC tPC Access time from address Read/Write cycle time Fast page mode cycle time 50 13 25 84 35 104 ns Power Dissipation, Refresh & Addressing: HYB 5116400 -50 Power Supply Addressing Refresh Active TTL Standby CMOS Standby 275 11 5.5 -60 5 V ± 10% 12/10 220 HYB 3116400 -50 -60 3.3 V ± 0.3 V 12/10 180 7.2 3.6 144 HYB 5117400 -50 -60 5 V ± 10% 11/11 440 11 5.5 385 HYB 3117400 -50 -60 3.3 V ± 0.3 V 11/11 288 7.2 3.6 252 mW mW mW 4096 cycles / 64 ms 2048 cycles / 32 ms Read, write, read-modify-write, CAS-before-RAS refresh, RAS-only refresh, hidden refresh and test mode All inputs, outputs and clocks fully TTL (5 V versions) and LV-TTL (3.3 V version)-compatible Plastic Package: P-SOJ-26/24-1 300 mil P-TSOPII-26/24-1 300 mil Semiconductor Group 1 1998-10-01 HYB 5116(7)400BJ-50/-60 HYB 3116(7)400BJ/BT-50/-60 4M × 4 DRAM The HYB 5(3)116(7)400 are 16 MBit dynamic RAMs based on die revisions “G” & “F” and organized as 4 194 304 words by 4-bits. The HYB 5(3)116(7)400BJ/BT utilizes a submicron CMOS silicon gate process technology, as well as advanced circuit techniques to provide wide operating margins, both inte...