HY64LD16162M

www.DataSheet4U.com HY64LD16162M Series Document Title 1M x 16 bit Low Low Power 1T/1C Pseudo SRAM Revision history Revision No. History 1.0 1.1 Initial Revised - Change Pin Connection - Improve tOE from 45ns to 30ns - Correct State Diagram 1.2 Revised - Correct Package Dimension - Change Absolute Maximum Ratings 1.3 Revised - DC Electrical Characteristics ( IDPD,ICC1) - State Diagram - Power Up Sequence - Deep Power Down Sequence - Read/Write Cycle Note 1.4 1.5 Revised - DC Electrical Characteristics ( ICC1: 3mA - > 5mA) Revised - Improve Standby Current ISB1 from 100uA to 80uA - Power Up Sequence 1.6 Revised - Improve ISB1 80uA to 75uA - Improve ICC2 30mA to 20mA - Improve Ambient Temperature C/E to E/I (0°C~85°C/-25°C~85°C → -25°C~85°C/-40°C~85°C) - Improve Maximum Absolute Ratings (Vdd : -0.3V to 3.3V → -0.3V to 3.6V) - Improve tOE 30ns to 20ns 1.7 Revised - Pin Description - Power Up & Deep Power Down Exit Sequence Mar. 11. ‘ 02 Final Feb. 27. ‘ 02 Preliminary Dec. 20. ‘ 01 Preliminary Nov. 14. ’ 01 Preliminary Oct. 07. ‘ 01 Preliminary Jul.18. ’ 01 Preliminary Draft Date Jan. 04. ’ 01 Jul. 03. ’ 01 Remark Preliminary Preliminary This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume any responsibility for use of circuits described. No patent licenses are implied. Revision 1.7 March. 2002 1 HY64LD16162M Series 1M x 16 bit Low Low Power 1T/1C SRAM DESCRIPTION The HY64LD16162M is a 16Mbit 1T/...