HY5PS1G821L

www.DataSheet4U.com HY5PS1G421(L)M HY5PS1G821(L)M 1Gb DDR2 SDRAM(DDP) HY5PS1G421(L)M HY5PS1G821(L)M This document is a general product description and is subject to change without notice. Hynix Electronics does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev 0.1 / Mar. 2004 1 www.DataSheet4U.com HY5PS1G421(L)M HY5PS1G821(L)M Revision Details Revision No. 0.1 Initial Release History Draft Date Mar.2003 Remark Preliminary Rev 0.1 / Mar. 2004 2 www.DataSheet4U.com HY5PS12421(L)F HY5PS12821(L)F HY5PS121621(L)F Contents 1. Description 1.1 Device Features and Ordering Information 1.1.1 Key Feaures 1.1.2 Ordering Information 1.1.3 Ordering Frequency 1.2 Pin configuration 1.2.1 256M × 4 DDR2 DDP Pin Configuration 1.2.2 128M × 8 DDR2 DDP Pin Configuration 1.3 Pin Description 2. Functioanal Description 2.1 Simplified State Diagram 2.2 Functional Block Diagram 2.2.1 Functional Block Diagram(256M × 4) 2.2.2 Functional Block Diagram(128M × 8) 2.3 Basic Function & Operation of DDR2 SDRAM 2.3.1 Power up and Initialization 2.3.2 Programming the Mode and Extended Mode Registers 2.3.2.1 DDR2 SDRAM Mode Register Set(MRS) 2.3.2.2 DDR2 SDRAM Extended Mode Register Set 2.3.2.3 Off-Chip Driver(OCD) Impedance Adjustment 2.3.2.4 ODT(On Die Termination) 2.4 Bank Activate Command 2.5 Read and Write Command 2.5.1 Posted CAS 2.5.2 Burst Mode Operation 2.5.3 Burst Read Command 2.5.4 Burst Write Operation 2.5.5 Write Data Mask 2.6 Precharge Operati...