HY5DU56422T

m o .c U 4 t e e h S a at .D w w w HY5DU56422(L)T HY5DU56822(L)T HY5DU561622(L)T m 2nd 256M DDR SDRAM o .c U 4 t e e h S a t a .D w w w HY5DU56422(L)T HY5DU56822(L)T HY5DU561622(L)T This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.7/May. 02 1 m o .c U 4 t e e h S a at .D w w w HY5DU56422(L)T HY5DU56822(L)T HY5DU561622(L)T Revision History 1. Revision 0.4 (Nov. 01) 1) Removed ‘Preliminary’ 2. Revision 0.5 (Dec. 01) 1) Separated ‘Function description’ and ‘Timing diagram’ parts - These are available in Web site (www.hynix.com) 3. Revision 0.6 (May. 02) 1) Input leakage current changed from +/-5uA to +/-2uA 4. Revision 0.7 (May. 02) 1) Added ‘tRAS Lock-out function supported’ Rev. 0.7/May. 02 2 HY5DU56422(L)T HY5DU56822(L)T HY5DU561622(L)T DESCRIPTION The Hynix HY5DU56422, HY5DU56822 and HY5DU561622 are a 268,435,456-bit CMOS Double Data Rate(DDR) Synchronous DRAM, ideally suited for the main memory applications which requires large memory density and high bandwidth. The Hynix 256Mb DDR SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the clock. While all addresses and control inputs are latched on the rising edges of the CK (falling edges of the /CK), Data, Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths...