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HY5DU283222Q Datasheet

Part Number HY5DU283222Q
Manufacturers Hynix Semiconductor
Logo Hynix Semiconductor
Description 128M(4Mx32) GDDR SDRAM
Datasheet HY5DU283222Q DatasheetHY5DU283222Q Datasheet (PDF)

www.DataSheet4U.com HY5DU283222Q 128M(4Mx32) GDDR SDRAM HY5DU283222Q This document is a general product description and is subject to change without notice. Hynix Electronics does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 1.2/Oct. 02 1 HY5DU283222Q Revision History No. History 1) Changed some AC parameters a) tAC : Changed from 0.7ns to 0.9ns b) tDQSCK : Changed from 0.6ns to 0.7ns c) tRCD/tRP : Changed from 4clks to 5clks at 222MHz an.

  HY5DU283222Q   HY5DU283222Q






Part Number HY5DU283222F
Manufacturers Hynix Semiconductor
Logo Hynix Semiconductor
Description 128M(4Mx32) GDDR SDRAM
Datasheet HY5DU283222Q DatasheetHY5DU283222F Datasheet (PDF)

www.DataSheet4U.com HY5DU283222F 128M(4Mx32) GDDR SDRAM HY5DU283222F This document is a general product description and is subject to change without notice. Hynix Electronics does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 1.2/Sep. 02 1 HY5DU283222F Rvision History Revision No. 0.4 History 1) Part Number changed from HY5DU283222F to HY6U22F 1) tAC/tDQSCK, tRCD/tRP parameters each speed changed as the followings a) tAC : changed from 0.7.

  HY5DU283222Q   HY5DU283222Q







Part Number HY5DU283222BFP
Manufacturers Hynix Semiconductor
Logo Hynix Semiconductor
Description 128M(4Mx32) GDDR SDRAM
Datasheet HY5DU283222Q DatasheetHY5DU283222BFP Datasheet (PDF)

HY5DU283222BF(P) 128M(4Mx32) GDDR SDRAM HY5DU283222BF(P) This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 1.0 / Feb. 2005 1 1HY5DU283222BF(P) Revision History No. History 0.1 1) Defined Target Spec. 0.2 1) Added 200MHz speed bin 0.3 1) Changed Cas Latency to 4 clock from 5 clock at 300Mhz/275Mhz/ 250Mhz speed bin 0.4 1) Changed ID.

  HY5DU283222Q   HY5DU283222Q







Part Number HY5DU283222BF
Manufacturers Hynix Semiconductor
Logo Hynix Semiconductor
Description 128M(4Mx32) GDDR SDRAM
Datasheet HY5DU283222Q DatasheetHY5DU283222BF Datasheet (PDF)

HY5DU283222BF(P) 128M(4Mx32) GDDR SDRAM HY5DU283222BF(P) This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 1.0 / Feb. 2005 1 1HY5DU283222BF(P) Revision History No. History 0.1 1) Defined Target Spec. 0.2 1) Added 200MHz speed bin 0.3 1) Changed Cas Latency to 4 clock from 5 clock at 300Mhz/275Mhz/ 250Mhz speed bin 0.4 1) Changed ID.

  HY5DU283222Q   HY5DU283222Q







Part Number HY5DU283222AF
Manufacturers Hynix Semiconductor
Logo Hynix Semiconductor
Description 128M(4Mx32) GDDR SDRAM
Datasheet HY5DU283222Q DatasheetHY5DU283222AF Datasheet (PDF)

www.DataSheet4U.com HY5DU283222AF 128M(4Mx32) GDDR SDRAM HY5DU283222AF This document is a general product description and is subject to change without notice. Hynix Electronics does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.7 / Jun. 2004 1 HY5DU283222AF Revision History Revision No. 0.1 0.11 0.2 0.3 Defined target spec. 500MHz speed bin added Defined IDD specification 1) Added 222MHz with CL3 and tCK_max=10ns at HY5DU283222AF-36 2) C.

  HY5DU283222Q   HY5DU283222Q







128M(4Mx32) GDDR SDRAM

www.DataSheet4U.com HY5DU283222Q 128M(4Mx32) GDDR SDRAM HY5DU283222Q This document is a general product description and is subject to change without notice. Hynix Electronics does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 1.2/Oct. 02 1 HY5DU283222Q Revision History No. History 1) Changed some AC parameters a) tAC : Changed from 0.7ns to 0.9ns b) tDQSCK : Changed from 0.6ns to 0.7ns c) tRCD/tRP : Changed from 4clks to 5clks at 222MHz and from 3clks to 4clks at 200/183MHz 1) 2) 3) 4) 0.5 Removed 166MHz part from speed bin Defined IDD specification Defined AC parameters of 250MHz part Changed Pin Capacitance a) Input Clock capacitance : Changed from 2/3pF to 1.7/2.7pF (min/max) b) All other Input-only pins capacitance : Changed from 2/3pF to 1.7/2.7pF (min/max) c) Input/Output capacitance (DQ, DQS, DM) : Changed from 4/5pF to 3.7/4.7pF (min/max) 5) Changed some AC parameters a) tIS/tIH : Changed from 0.9ns to 1.0ns b) tDS/tDH : Changed from 0.45ns to 0.5ns 6) Changed VIH/VIL from Vref +/- 0.31V to Vref +/- 0.35V 1) Changed VIH/VIL from Vref +/- 0.35V to Vref +/- 0.45V 2) Change tCK_max from 5.5ns to 6ns at 250/222MHz and from 10ns to 7ns at 200/183MHz 1) Changed some AC parameters a) tQHS : Changed from 0.75ns to 0.45ns at 200/183MHz b) tDS/tDH : Changed from 0.5ns to 0.45ns 1) tRCD/tRP of 3clocks at 183/200MHz at single bank operation defined 2) tCK Max of 200/183MHz part changed from 7ns to 8ns 1) Power dissipation S.


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