● Standard SDRAM Protocol ● Internal 4bank operation ● Power Supply Voltage : VDD = 3.3V, VDDQ = 3.3V ● All device pins are compatible with LVTTL interface ● Low Voltage interface to reduce I/O power ● 8,192 Refresh cycles / 64ms ● Programmable CAS ...
HY57V561620FLT-H PDF File
