HD74LV573A
Octal D-type Transparent Latches with 3-state Outputs
ADE-205-279A (Z) 2nd Edition July 1999 Description
The...
HD74LV573A
Octal D-type Transparent Latches with 3-state Outputs
ADE-205-279A (Z) 2nd Edition July 1999 Description
The HD74LV573A has eight D-type latches with three-state outputs in a 20-pin package. When the latch enable input is high, the Q outputs will follow the D inputs. When the latch enable goes low, data at the D inputs will be retained at the outputs until latch enable returns high again. When a high logic level is applied to the output control input, all outputs go to a high impedance state, regardless of what signals are present at the other inputs and the state of the storage elements. Low-
voltage and high-speed operation is suitable for the battery-powered products (e.g., notebook computers), and the low-power consumption extends the battery life.
Features
VCC = 2.0 V to 5.5 V operation All inputs VIH (Max.) = 5.5 V (@VCC = 0 V to 5.5 V) All outputs VO (Max.) = 5.5 V (@VCC = 0 V) Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C) Typical VOH undershoot > 2.3 V (@VCC = 3.3 V, Ta = 25°C) Output current ±8 mA (@VCC = 3.0 V to 3.6 V), ±16 mA (@VCC = 4.5 V to 5.5 V)
Function Table
Inputs OE L L L H Note: H: L: X: Z: Q0 : LE H H L X D H L X X Output Q H L Q0 Z
High level Low level Immaterial High impedance Output level before the indicated steady state input conditions were established
HD74LV573A
Pin Arrangement
OE 1 1D 2 2D 3 3D 4 4D 5 5D 6 6D 7 7D 8 8D 9 GND 10
20 VCC 19 1Q 18 2Q 17 3Q 16 4Q 15 5Q 14 6Q 13 7Q 12 8Q 11 LE
(Top view)
2
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