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Manufacture Part Number Description PDF
Hitachi Semiconductor
Hitachi Semiconductor
HD74LS27 Triple 3-input Positive NOR Gates
Unit: mm
19.20 20.32 Max 14 8 6.30 7.40 Max 1
2.39 Max

1.30

7 7.62

0.51 Min

2.54 Min 5.06 Max

2.54 ± 0.25

0.48 ± 0.10

0.25 – 0.05 0° – 15°

+ 0.10

Hitachi Code JEDEC EIAJ Weight (refer
HD74LS27 pdf
Renesas
Renesas
HD74LS27 Triple 3-input Positive NOR Gates
HD74LS27
Triple 3-input Positive NOR Gates

Features
• Ordering Information

Part Name

Package Type

Package Code Package (Previous Code) Abbreviation

HD74LS27P

DILP-14 pin

PRDP0014AB-B (DP-14AV
HD74LS27 pdf
Hitachi Semiconductor
Hitachi Semiconductor
HD74LS273 Octal D-type Positive-edge-triggered Flip-Flops(with Clear)
Unit: mm

24.50 25.40 Max 20 11 7.00 Max 6.30 1 0.89
1.27 Max

10 1.30 2.54 Min 5.08 Max 7.62

0.51 Min

2.54 ± 0.25

0.48 ± 0.10

0.25 – 0.05 0° – 15°

+ 0.11

Hitachi Code JEDEC EIAJ Weight 
HD74LS27 pdf
Renesas
Renesas
HD74LS273 Octal D-type Positive-edge-triggered Flip-Flops
HD74LS273

Octal D-type Positive-edge-triggered Flip-Flops (with Clear)
REJ03D0473–0300 Rev.3.00
Jul.15.2005

The HD74LS273, positive-edge-triggered flip-flops utilize LS TTL circuitry to implement 
HD74LS27 pdf
Hitachi Semiconductor
Hitachi Semiconductor
HD74LS279 Quadruple S-R Latches
19.20 20.00 Max 16 9 7.40 Max 6.30

Unit: mm

1 1.3
1.11 Max

8

0.51 Min

2.54 Min 5.06 Max

7.62

2.54 ± 0.25

0.48 ± 0.10

0.25 – 0.05 0° – 15°
Hitachi Code JEDEC EIAJ Weight (reference val
HD74LS27 pdf
Renesas
Renesas
HD74LS279 Quadruple S-R Latches
HD74LS279
Quadruple S-R Latches

Features
• Ordering Information

Part Name

Package Type

Package Code (Previous Code)

Package Abbreviation

HD74LS279P

DILP-16 pin

PRDP0016AE-B (DP-16FV)

P

HD7
HD74LS27 pdf





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