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(PDF) HD74LS10 Datasheet download


Manufacture Part Number Description PDF
Hitachi Semiconductor
Hitachi Semiconductor
HD74LS10 Triple 3-input Positive NAND Gates
Unit: mm
19.20 20.32 Max 14 8 6.30 7.40 Max 1
2.39 Max

1.30

7 7.62

0.51 Min

2.54 Min 5.06 Max

2.54 ± 0.25

0.48 ± 0.10

0.25 – 0.05 0° – 15°

+ 0.10

Hitachi Code JEDEC EIAJ Weight (refer
HD74LS10 pdf
Renesas
Renesas
HD74LS10 Triple 3-Input Positive NAND Gates
HD74LS10
Triple 3-Input Positive NAND Gates

Features
• Ordering Information

Part Name

Package Type

Package Code (Previous Code)

Package Abbreviation

HD74LS10P

DILP-14 pin

PRDP0014AB-B (DP-14
HD74LS10 pdf
Hitachi Semiconductor
Hitachi Semiconductor
HD74LS107A Dual J-K Negative-edge-triggered Flip-Flops(with Clear)
Unit: mm
19.20 20.32 Max 14 8 6.30 7.40 Max 1
2.39 Max

1.30

7 7.62

0.51 Min

2.54 Min 5.06 Max

2.54 ± 0.25

0.48 ± 0.10

0.25 – 0.05 0° – 15°

+ 0.10

Hitachi Code JEDEC EIAJ Weight (refer
HD74LS10 pdf
Renesas
Renesas
HD74LS107A Dual J-K Negative-edge-triggered Flip-Flops
HD74LS107A

Dual J-K Negative-edge-triggered Flip-Flops (with Clear)
REJ03D0425–0300 Rev.3.00
Jul.13.2005
Features
• Ordering Information

Part Name

Package Type

Package Code (Previous Code)

Pa
HD74LS10 pdf
Hitachi Semiconductor
Hitachi Semiconductor
HD74LS109 Dual J-K Positive-edge-triggered Flip-Flops(with Preset and Clear)
19.20 20.00 Max 16 9 7.40 Max 6.30

Unit: mm

1 1.3
1.11 Max

8

0.51 Min

2.54 Min 5.06 Max

7.62

2.54 ± 0.25

0.48 ± 0.10

0.25 – 0.05 0° – 15°
Hitachi Code JEDEC EIAJ Weight (reference val
HD74LS10 pdf
Hitachi Semiconductor
Hitachi Semiconductor
HD74LS109A Dual J-K Positive-edge-triggered Flip-Flops(with Preset and Clear)
19.20 20.00 Max 16 9 7.40 Max 6.30

Unit: mm

1 1.3
1.11 Max

8

0.51 Min

2.54 Min 5.06 Max

7.62

2.54 ± 0.25

0.48 ± 0.10

0.25 – 0.05 0° – 15°
Hitachi Code JEDEC EIAJ Weight (reference val
HD74LS10 pdf





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