HD74HC113

HD74HC113 Dual J-K Flip-Flops (with Preset) Description This flip-flop is edge sensitive to the clock input and change state on the negative going transition of the clock pulse. Each one has independent J, K, clock, and preset inputs and Q and Q inputs. Preset is independent of the clock and accomplished by a low level on the input. Features High Speed Operation: tpd (Clock to Q) = 18 ns typ (CL = 50 pF) High Output Current: Fanout of 10 LSTTL Loads Wide Operating Voltage: VCC = 2 to 6 V Low Input Current: 1 µA max Low Quiescent Supply Current: ICC (static) = 2 µA max (Ta = 25°C) Function Table Inputs Preset L H H H H H H H H L Clock X J X L L H H X X X K X L H L H X X X Output Q H No change L H Toggle No change No change No change H L Q L HD74HC113 Pin Arrangement 1CK 1K 1J 1PR 1Q 1Q GND 1 2 3 4 5 Q 6 7 (Top view) CK PR Q J K 14 VCC 13 2CK 12 2K 11 2J Q K CK PR Q 9 8 2Q 2Q J 10 2PR Logic Diagram (1/2) CLR J K # CK CK # CK CK CK CK Q Q # CK # CK # CK CK CK 2 HD74HC113 DC Characteristics Ta = 25°C Item Input voltage Symbol VIH Ta = –40 to +85°C Max — — — 0.5 1.35 1.8 — — — — — 0.1 0.1 0.1 0.33 0.33 ±1.0 20 µA µA I OL = 4 mA I OL = 5.2 mA Vin = VCC or GND Vin = VCC or GND, Iout = 0 µA V I OH = –4 mA I OH = –5.2 mA Vin = VIH or VIL I OL = 20 µA V Vin = VIH or VIL I OH = –20 µA V Unit V Test Conditions VCC (V) Min Typ Max Min 2.0 4.5 6.0 1.5 — 3.15 — 4.2 — — — — — — — — — — 0.5 1.5 3.15 4.2 — VIL 2.0 4.5 6.0 1.35 — 1.8 — 1.9 4.4 5.9 4.13 5.63 — — — ...