HD74ALVC16834

HD74ALVC16834 18-bit Universal Bus Driver with 3-state Outputs and Inverted Latch Enable ADE-205-216D (Z) 5th. Edition December 1999 Description The HD74ALVC16834 is an 18-bit universal bus driver designed for 2.3 V to 3.6 V VCC operation. Data flow from A to Y is controlled by output enable (OE). The device operates in the transparent mode when the latch enable ( LE) input is low. The A data is latched if the clock (CLK) input is held at a high or low logic level. If LE is high, the A data is stored in the latch/flip flop on the low to high transition of the CLK. When OE is high, the outputs are in the high impedance state. To ensure the high impedance state during power up or power down, OE should be tied to V CC through a pullup registor; the minimum value of the registor is determined by the current sinking capability of the driver. Features Meets “PC SDRAM registered DIMM design support document, Rev. 1.2” Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C) Typical VOH undershoot > 2.0 V (@VCC = 3.3 V, Ta = 25°C) High output current ±24 mA (@V CC = 3.0 V) HD74ALVC16834 Function Table Inputs OE H L L L L L L H: L: X: Z: ↑: Notes: LE X L L H H H H CLK X X X ↑ ↑ H L A X L H L H X X Output Y Z L H L H Y0 *1 Y0 *2 High level Low level Immaterial High impedance Low to high transition 1. Output level before the indicated steady-state input conditions were established, provided that CLK was high before LE went low. 2. Output level before the indicated steady-...