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GM71V18160C Datasheet

Part Number GM71V18160C
Manufacturers Hynix Semiconductor
Logo Hynix Semiconductor
Description (GM71VS18160CL / GM71VS18160C) 1M x 16-Bit CMOS DRAM
Datasheet GM71V18160C DatasheetGM71V18160C Datasheet (PDF)

GM71V18160C GM71VS18160CL 1,048,576 WORDS x 16 BIT CMOS DYNAMIC RAM Description The GM71V(S)18160C/CL is the new generation dynamic RAM organized 1,048,576 x 16 bit. GM71V(S)18160C/CL has realized higher density, higher performance and various functions by utilizing advanced CMOS process technology. The GM71V(S)18160C/CL offers Fast Page Mode as a high speed access mode. Multiplexed address inputs permit the GM71V(S)18160C/CL to be packaged in standard 400 mil 42pin plastic SOJ, and standard 40.

  GM71V18160C   GM71V18160C






(GM71VS18160CL / GM71VS18160C) 1M x 16-Bit CMOS DRAM

GM71V18160C GM71VS18160CL 1,048,576 WORDS x 16 BIT CMOS DYNAMIC RAM Description The GM71V(S)18160C/CL is the new generation dynamic RAM organized 1,048,576 x 16 bit. GM71V(S)18160C/CL has realized higher density, higher performance and various functions by utilizing advanced CMOS process technology. The GM71V(S)18160C/CL offers Fast Page Mode as a high speed access mode. Multiplexed address inputs permit the GM71V(S)18160C/CL to be packaged in standard 400 mil 42pin plastic SOJ, and standard 400mil 44(50)pin plastic TSOP II. The package size provides high system bit densities and is compatible with widely available automated testing and insertion equipment. Features * 1,048,576 Words x 16 Bit Organization * Fast Page Mode Capability * Single Power Supply (3V+/-0.3V) * Fast Access Time & Cycle Time (Unit: ns) tRAC tCAC GM71V(S)18160C/CL-5 GM71V(S)18160C/CL-6 GM71V(S)18160C/CL-7 50 60 70 13 15 18 tRC 90 110 130 tPC 35 40 45 Pin Configuration 42 SOJ VCC I/O0 I/O1 I/O2 I/O3 VCC I/O4 I/O5 I/O6 I/O7 NC NC WE RAS NC NC A0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 * Low Power Active : 684/612/540/468mW (MAX) Standby : 7.2mW (CMOS level : MAX) 0.54mW (L-version : MAX) * RAS Only Refresh, CAS before RAS Refresh, Hidden Refresh Capability * All inputs and outputs TTL Compatible * 1024 Refresh Cycles/16ms * 1024 Refresh Cycles/128ms (L-version) * Self Refresh Operation (L-version) * Battery Back Up Operation (L-version) * 2.


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