FAS209

www.DataSheet4U.com QLogic Corporation FAS209 Fast Architecture SCSI Data Sheet Features s s s s s s s s s s s s s s s s s s s Compliance with ANSI SCSI-2 standard X3.131-1994 and SCSI-1 Compliance with ANSI X3T10/855D SCSI-3 parallel interface (SPI) standard Compliance with ANSI SCSI configured automatically (SCAM) protocol levels 1 and 2 Synchronous data transfers up to 10 Mbytes/sec fast SCSI and 5 Mbytes/sec normal SCSI Asynchronous data transfers up to 7 Mbytes/sec Up to 12 Mbytes/sec DMA burst transfer rate Clock rates up to 40 MHz Supports hot plugging Programmable active negation Low-input capacitance Programmable split-bus architecture DMA interface options Two bus configurations On-chip, 48-mA, single-ended drivers and receivers Parity pass-through on FIFO data Initiator and target roles SCSI sequences implemented without microprocessor intervention Part-unique ID code Eight-bit, single-ended SCSI operations bus, minimizing board space requirements. The FAS209’s highly integrated structure provides users with numerous benefits. Initiator and target roles are supported; therefore, the FAS209 can be used in both host adapter and peripheral applications. The FAS209 performs such functions as bus arbitration, selection of a target, or reselection of an initiator. It handles message, command, status, and data transfer between the SCSI bus and the chip’s 16-byte internal FIFO or a buffer memory. The above functions are internal processes performed by the FAS209 chip with...