EPM7128B

www.DataSheet4U.com MAX 7000B ® Programmable Logic Device Data Sheet September 2003, ver. 3.4 Features... ■ ■ High-performance 2.5-V CMOS EEPROM-based programmable logic devices (PLDs) built on second-generation Multiple Array MatriX (MAX®) architecture (see Table 1) – Pin-compatible with the popular 5.0-V MAX 7000S and 3.3-V MAX 7000A device families – High-density PLDs ranging from 600 to 10,000 usable gates – 3.5-ns pin-to-pin logic delays with counter frequencies in excess of 303.0 MHz Advanced 2.5-V in-system programmability (ISP) – Programs through the built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface with advanced pin-locking capability – Enhanced ISP algorithm for faster programming – ISP_Done bit to ensure complete programming – Pull-up resistor on I/O pins during in-system programming – ISP circuitry compliant with IEEE Std. 1532 f For information on in-system programmable 5.0-V MAX 7000S or 3.3-V MAX 7000A devices, see the MAX 7000 Programmable Logic Device Family Data Sheet or the MAX 7000A Programmable Logic Device Family Data Sheet. Table 1. MAX 7000B Device Features Feature Usable gates Macrocells Logic array blocks Maximum user I/O pins tPD (ns) tSU (ns) tFSU (ns) tCO1 (ns) fCNT (MHz) EPM7032B 600 32 2 36 3.5 2.1 1.0 2.4 303.0 EPM7064B 1,250 64 4 68 3.5 2.1 1.0 2.4 303.0 EPM7128B 2,500 128 8 100 4.0 2.5 1.0 2.8 243.9 EPM7256B 5,000 256 16 164 5.0 3.3 1.0 3.3 188.7 EPM7512B 10,000 512 32 212 5.5 3.6 1.0 3.7 163.9 Altera Corporat...