CMOS Gate Array
Core Logic
(1[
$0,+* PLFURQ &026 *DWH $UUD\
Description EN2x is a family of 2-input gates which perform the log...
Description
Core Logic
(1[
$0,+* PLFURQ &026 *DWH $UUD\
Description EN2x is a family of 2-input gates which perform the logical exclusive NOR (XNOR) function.
Logic Symbol
Truth Table
EN2x
A Q
B
ABQ L LH LHL HL L HHH
HDL Syntax Verilog .................... EN2x inst_name (Q, A, B); VHDL...................... inst_name: EN2x port map (Q, A, B);
Pin Loading
Pin Name A B
EN21 2.1 2.1
EN22 4.2 4.2
Equivalent Loads EN23 4.2 4.2
EN24 4.3 4.3
Size And Power Characteristics
Power Characteristicsa
Cell Equivalent Gates
Static IDD (TJ = 85°C) (nA)
EQLpd (Eq-load)
EN21 EN22
3.0 5.0
TBD TBD
3.9 8.8
EN23 EN24 EN26
7.0 8.0 8.0
TBD TBD TBD
12.9 14.6 18.4
a. See page 2-15 for power equation.
EN26 4.2 4.3
3-118
®
Core Logic
(1[
®
Propagation Delays (ns)
Conditions: TJ = 25°C, VDD = 5.0V, Typical Process
EN21
Number of Equivalent Loads
From: Any Input To: Q
tPLH tPHL
Number of Equivalent Loads
1
0.29 0.19
1
2
0.33 0.25
4
EN22
From: Any Input To: Q
tPLH tPHL
0....
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