P-Channel Logic Level Enhancement Mode Field Effect Transistor
Description
P‐Channel Logic Level Enhancement Mode Field Effect Transistor
Product Summary:
BVDSS
‐20V
D
RDSON (MAX.)
25mΩ
ID
‐7.8A
G
S
Pb‐Free Lead Plating & Halogen Free
ABSOLUTE MAXIMUM RATINGS (TA = 25 °C Unless Otherwise Noted)
PARAMETERS/TEST CONDITIONS
Bottom View
S DD
SD
GD D
PIN 1
SYMBOL
EMF25P02VA
LIMITS
UNIT
Gate‐Sour...
