Dual N‐Channel Logic Level Enhancement Mode Field Effect Transistor
Product Summary:
N‐CH‐Q1 N‐CH‐Q2
BVDSS ...
Dual N‐Channel Logic Level Enhancement Mode Field Effect Transistor
Product Summary:
N‐CH‐Q1 N‐CH‐Q2
BVDSS RDSON (MAX.)
30V 12mΩ
30V 17mΩ
ID 12A 10A
UIS, Rg 100% Tested
Pb‐Free Lead Plating & Halogen Free
ABSOLUTE MAXIMUM RATINGS (TA = 25 °C Unless Otherwise Noted)
PARAMETERS/TEST CONDITIONS
SYMBOL
Gate‐Source
Voltage
Continuous Drain Current Pulsed Drain Current1
TA = 25 °C TA = 100 °C
Avalanche Current
Avalanche Energy Repetitive Avalanche Energy2
L = 0.1mH, ID=12A, RG=25Ω
L = 0.05mH
Power Dissipation
TA = 25 °C TA = 100 °C
Operating Junction & Storage Temperature Range
VGS ID
IDM IAS EAS EAR PD
Tj, Tstg
EMB12K03V
LIMITS
Q1 Q2
±20 ±20
12 10
8.5 7
48 40
12 12
7.2 7.2
3.6 3.6
2.00
2.00
0.8 0.8 ‐55 to 150
UNIT V A
mJ ...