DATA SHEET
64M bits SDRAM
EDS6416AHBH, EDS6416CHBH (4M words × 16 bits)
Description
The EDS6416AHBH, EDS6416CHBH are 64...
DATA SHEET
64M bits SDRAM
EDS6416AHBH, EDS6416CHBH (4M words × 16 bits)
Description
The EDS6416AHBH, EDS6416CHBH are 64M bits SDRAMs organized as 1,048,576 words × 16 bits × 4 banks. All inputs and outputs are synchronized with www.DataSheet4U.com the positive edge of the clock. Supply
voltages are 3.3V (EDS6416AHBH) and 2.5V (EDS6416CHBH). It is packaged in 60-ball FBGA.
Pin Configurations
/xxx indicate active low signal.
60-ball FBGA
1 A VSS B
DQ15 DQ0 VDD
2
3
4
5
6
7
Features
3.3V and 2.5V power supply Clock frequency: 166MHz/133MHz (max.) Single pulsed /RAS ×16 organization 4 banks can operate simultaneously and independently Burst read/write operation and burst read/single write operation capability 2 variations of burst sequence Sequential (BL = 1, 2, 4, 8, full page) Interleave (BL = 1, 2, 4, 8) Programmable /CAS latency (CL): 2, 3 Byte control by UDQM and LDQM Refresh cycles: 4096 refresh cycles/64ms 2 variations of refresh Auto refresh Self refresh FBGA package with lead free solder (Sn-Ag-Cu) RoHS compliant
C
DQ14
VSSQ
VDDQ
DQ1
DQ13 VDDQ
VSSQ
DQ2
D
DQ12 DQ11 DQ4 DQ3
E
DQ10 VSSQ VDDQ DQ5
F
DQ9 VDDQ VSSQ DQ6
G
DQ8 NC NC DQ7
H
NC VSS VDD NC
J
NC UDQM LDQM /WE
K
NC CLK /RAS /CAS
L
CKE NC NC /CS
M
A11 A9 BA1 BA0
N
A8 P A6 R VSS A4 A3 VDD A5 A2 A1 A7 A0 A10
(Top view)
A0 to A11 BA0, BA1 DQ0 to DQ15 /CS /RAS /CAS /WE LDQM, UDQM Address input Bank select address Data-input/output Chip select Row address strobe Col...