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EDE1108AASE Datasheet

Part Number EDE1108AASE
Manufacturers Elpida Memory
Logo Elpida Memory
Description (EDE1104AASE / EDE1108AASE) 1G bits DDR2 SDRAM organized
Datasheet EDE1108AASE DatasheetEDE1108AASE Datasheet (PDF)

www.DataSheet4U.com DATA SHEET 1G bits DDR2 SDRAM EDE1104AASE (256M words × 4 bits) EDE1108AASE (128M words × 8 bits) Description The EDE1104AASE is a 1G bits DDR2 SDRAM organized as 33,554,432 words × 4 bits × 8 banks. The EDE1108AASE is a 1G bits DDR2 SDRAM organized as 16,777,216 words × 8 bits × 8 banks. They are packaged in 68-ball FBGA (µBGA) package. Features • Power supply: VDD, VDDQ = 1.8V ± 0.1V • Double-data-rate architecture: two data transfers per clock cycle • Bi-directional, d.

  EDE1108AASE   EDE1108AASE






(EDE1104AASE / EDE1108AASE) 1G bits DDR2 SDRAM organized

www.DataSheet4U.com DATA SHEET 1G bits DDR2 SDRAM EDE1104AASE (256M words × 4 bits) EDE1108AASE (128M words × 8 bits) Description The EDE1104AASE is a 1G bits DDR2 SDRAM organized as 33,554,432 words × 4 bits × 8 banks. The EDE1108AASE is a 1G bits DDR2 SDRAM organized as 16,777,216 words × 8 bits × 8 banks. They are packaged in 68-ball FBGA (µBGA) package. Features • Power supply: VDD, VDDQ = 1.8V ± 0.1V • Double-data-rate architecture: two data transfers per clock cycle • Bi-directional, differential data strobe (DQS and /DQS) is transmitted/received with data, to be used in capturing data at the receiver • DQS is edge aligned with data for READs: centeraligned with data for WRITEs • Differential clock inputs (CK and /CK) • DLL aligns DQ and DQS transitions with CK transitions • Commands entered on each positive CK edge: data and data mask referenced to both edges of DQS • 8 internal banks for concurrent operation • Data mask (DM) for write data • Burst lengths: 4, 8 • /CAS Latency (CL): 3, 4, 5 • Auto precharge operation for each burst access • Auto refresh and self refresh modes • Average refresh period  7.8µs at 0°C ≤ TC ≤ +85°C  3.9µs at +85°C < TC ≤ +95°C • SSTL_18 compatible I/O • Posted CAS by programmable additive latency for better command and data bus efficiency • Off-Chip-Driver Impedance Adjustment and On-DieTermination for better signal quality • Programmable RDQS, /RDQS output for making × 8 organization compatible to × 4 organization • /DQS, (/RDQS) can.


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