DS90CF384AQ

DS90CF384AQ www.ti.com SNLS345A – AUGUST 2011 – REVISED APRIL 2013 DS90CF384AQ +3.3V LVDS Receiver 24-Bit Flat Panel Display (FPD) Link - 65 MHz Check for Samples: DS90CF384AQ FEATURES 1 2 Automotive Grade Device, AEC-Q100 Grade 3 Qualified Operating Temperature Range: –40°C to +85°C 20 to 65 MHz Shift Clock Support 50% Duty Cycle on Receiver Output Clock Best–in–Class Set & Hold Times on RxOUTPUTs Rx Power Consumption <142 mW (typ) @65MHz Grayscale Rx Power-down Mode <200μW (max) ESD Rating >7 kV (HBM), >700V (EIAJ) Supports VGA, SVGA, XGA and Dual Pixel SXGA. PLL Requires No External Components Compatible with TIA/EIA-644 LVDS Standard Low Profile 56-Lead TSSOP Package DESCRIPTION The DS90CF384AQ receiver converts the four LVDS data streams at up to 1.8 Gbps throughput (227 Megabytes/sec bandwidth) back into parallel 28 bits of LVCMOS/LVTTL data. In a Display application, the 28 bits include: 24 bits of RGB data and up to 4 bits of video control (Hsync, Vsync, DE and CNTL). The DS90CF384AQ device is enhanced over prior generation FPD-Link receivers, provides a wider data valid time on the receiver output and is offered as an AEC-Q100 grade 3 device. FPD-Link is an ideal means to solve EMI and cable size problems associated with wide, high speed LVCMOS/LVTTL interfaces. Block Diagram Figure 1. DS90CF384AQ Block Diagram 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texa...