DS31406

ABRIDGED DATA SHEET 19-5711; Rev 0; 12/10 DS31406 2-Input, 14-Output, Single DPLL Timing IC with Sub-ps Output Jitter General Description The DS31406 is a flexible, high-performance timing IC for diverse frequency conversion and frequency synthesis applications. On each of its two input clocks and fourteen output clocks, the device can accept or generate nearly any frequency between 2kHz and 750MHz. The input clocks are divided down, fractionally scaled as needed, and continuously monitored for activity and frequency accuracy. The best input clock is selected, manually or automatically, as the reference clock for the rest of the device. A flexible, high-performance digital PLL locks to the selected reference and provides programmable bandwidth, very high resolution holdover capability, and truly hitless switching between input clocks. The digital PLL is followed by a clock synthesis subsystem which has seven fully programmable digital frequency synthesis blocks, three high-speed low-jitter APLLs, and 14 output clocks, each with its own 32-bit divider and phase adjustment. The APLLs provide fractional scaling and output jitter less than 1ps RMS. For telecom systems, the DS31406 has all required features and functions to serve as a central timing function or as a line card timing IC. With a suitable oscillator the DS31406 meets the requirements of Stratum 2, 3E, 3, 4E, and 4, G.812 Types I–IV, G.813, and G.8262. Features  Two Input Clocks       Differential or CMOS/TTL...