DM74S257

DM74S257 3-STATE Quad 1-of-2 Data Selector/Multiplexer August 1986 Revised May 2000 DM74S257 3-STATE Quad 1-of-2 Data Selector/Multiplexer General Description These Schottky-clamped high-performance multiplexers feature 3-STATE outputs that can interface directly with data lines of bus-organized systems. With all but one of the common outputs disabled (at a high impedance state), the low impedance of the single enabled output will drive the bus line to a HIGH or LOW logic level. To minimize the possibility that two outputs will attempt to take a common bus to opposite logic levels, the output enable circuitry is designed such that the output disable times are shorter than the output enable times. This 3-STATE output feature means that n-bit (paralleled) data selectors with up to 258 sources can be implemented for data buses. It also permits the use of standard TTL registers for data retention throughout the system. Features s 3-STATE versions S157, S158, with same pin-outs s Schottky-clamped for significant improvement in A-C performance s Provides bus interface from multiple sources in high-performance systems s Average propagation delay from data input s Typical power dissipation 4.8 ns 320 mW Ordering Code: Order Number DM74S257N Package Number N16E Package Description 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Connection Diagram Function Table Inputs Output Control H L L L L H = HIGH Level L = LOW Level X = Don’t Care Z = High Impedance (O...