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DM74LS75 Datasheet

Part Number DM74LS75
Manufacturers Fairchild Semiconductor
Logo Fairchild Semiconductor
Description Quad Latch
Datasheet DM74LS75 DatasheetDM74LS75 Datasheet (PDF)

DM74LS75 Quad Latch August 1986 Revised March 2000 DM74LS75 Quad Latch General Description These latches are ideally suited for use as temporary storage for binary information between processing units and input/output or indicator units. Information present at a data (D) input is transferred to the Q output when the enable is HIGH, and the Q output will follow the data input as long as the enable remains HIGH. When the enable goes LOW, the information (that was present at the data input at the.

  DM74LS75   DM74LS75






Part Number DM74LS74A
Manufacturers Fairchild Semiconductor
Logo Fairchild Semiconductor
Description Dual Positive-Edge-Triggered D Flip-Flops
Datasheet DM74LS75 DatasheetDM74LS74A Datasheet (PDF)

DM74LS74A Dual Positive-Edge-Triggered D Flip-Flops with Preset, Clear and Complementary Outputs August 1986 Revised March 2000 DM74LS74A Dual Positive-Edge-Triggered D Flip-Flops with Preset, Clear and Complementary Outputs General Description This device contains two independent positive-edge-triggered D flip-flops with complementary outputs. The information on the D input is accepted by the flip-flops on the positive going edge of the clock pulse. The triggering occurs at a voltage level an.

  DM74LS75   DM74LS75







Part Number DM74LS74A
Manufacturers National Semiconductor
Logo National Semiconductor
Description Dual Positive-Edge-Triggered D Flip-Flops
Datasheet DM74LS75 DatasheetDM74LS74A Datasheet (PDF)

54LS74 DM54LS74A DM74LS74A Dual Positive-Edge-Triggered D Flip-Flops with Preset Clear and Complementary Outputs June 1989 54LS74 DM54LS74A DM74LS74A Dual Positive-Edge-Triggered D Flip-Flops with Preset Clear and Complementary Outputs General Description This device contains two independent positive-edge-triggered D flip-flops with complementary outputs The information on the D input is accepted by the flip-flops on the positive going edge of the clock pulse The triggering occurs at a voltage.

  DM74LS75   DM74LS75







Part Number DM74LS73A
Manufacturers Fairchild Semiconductor
Logo Fairchild Semiconductor
Description Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops
Datasheet DM74LS75 DatasheetDM74LS73A Datasheet (PDF)

DM74LS73A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Clear and Complementary Outputs August 1986 Revised March 2000 DM74LS73A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Clear and Complementary Outputs General Description This device contains two independent negative-edge-triggered J-K flip-flops with complementary outputs. The J and K data is processed by the flip-flops on the falling edge of the clock pulse. The clock triggering occurs at a voltage level .

  DM74LS75   DM74LS75







Part Number DM74LS73A
Manufacturers National Semiconductor
Logo National Semiconductor
Description DUAL NEGATIVE-EDGE-TRIGGERED MASTER-SLAVE J-K FLIP-FLOPS
Datasheet DM74LS75 DatasheetDM74LS73A Datasheet (PDF)

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  DM74LS75   DM74LS75







Quad Latch

DM74LS75 Quad Latch August 1986 Revised March 2000 DM74LS75 Quad Latch General Description These latches are ideally suited for use as temporary storage for binary information between processing units and input/output or indicator units. Information present at a data (D) input is transferred to the Q output when the enable is HIGH, and the Q output will follow the data input as long as the enable remains HIGH. When the enable goes LOW, the information (that was present at the data input at the time the transition occurred) is retained at the Q output until the enable is permitted to go HIGH. These latches feature complementary Q and Q outputs from a 4-bit latch, and are available in 16-pin packages. Ordering Code: Order Number DM74LS75M DM74LS75N Package Number M16A N16E Package Description 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Diagram (Each Latch) Connection Diagram Function Table Inputs D L H X (Each Latch) Outputs Q L H Q0 Q H L Q0 Enable H H L H = HIGH Level L = LOW Level X = Don't Care Q0 = The Level of Q Before the HIGH-to-LOW Transition of ENABLE © 2000 Fairchild Semiconductor Corporation DS006374 www.fairchildsemi.com DM74LS75 Absolute Maximum Ratings(Note 1) Supply Voltage Input Voltage Operating Free Air Temperature Range Storage Tempe.


2006-01-20 : TSOP34838    TSOP34830    TSOP34833    TSOP34836    TSOP34837    TSOP34840    TSOP34856    DM74LS75    DM74LS74A    DM74LS74A   


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