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DM74AS169A Datasheet

Part Number DM74AS169A
Manufacturers Fairchild Semiconductor
Logo Fairchild Semiconductor
Description Synchronous 4-Bit Binary Up/Down Counter
Datasheet DM74AS169A DatasheetDM74AS169A Datasheet (PDF)

DM74AS169A Synchronous 4-Bit Binary Up/Down Counter April 1984 Revised March 2000 DM74AS169A Synchronous 4-Bit Binary Up/Down Counter General Description These synchronous presettable counters feature an internal carry look ahead for cascading in high speed counting applications. The DM74AS169 is a 4-bit binary up/down counter. The carry output is decoded to prevent spikes during normal mode of counting operation. Synchronous operation is provided so that outputs change coincident with each ot.

  DM74AS169A   DM74AS169A






Synchronous 4-Bit Binary Up/Down Counter

DM74AS169A Synchronous 4-Bit Binary Up/Down Counter April 1984 Revised March 2000 DM74AS169A Synchronous 4-Bit Binary Up/Down Counter General Description These synchronous presettable counters feature an internal carry look ahead for cascading in high speed counting applications. The DM74AS169 is a 4-bit binary up/down counter. The carry output is decoded to prevent spikes during normal mode of counting operation. Synchronous operation is provided so that outputs change coincident with each other when so instructed by count enable inputs and internal gating. This mode of operation eliminates the output counting spikes which are normally associated with asynchronous (ripple clock) counters. A buffered clock input triggers the four flip-flops on the rising (positive going) edge of clock input waveform. These counters are fully programmable; that is, the outputs may each be preset either HIGH or LOW. The load input circuitry allows loading with carry-enable output of cascaded counters. As loading is synchronous, setting up a LOW level at the load input disables the counter and causes the outputs to agree with the data inputs after the next clock pulse. The carry look-ahead circuitry permits cascading counters for n-bit synchronous applications without additional gating. Both count enable inputs (P and T) must be LOW to count. The direction of the count is determined by the level of the up/down input. When the input is HIGH, the counter counts UP; when LOW, it counts DOWN. Inpu.


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