Quad 3-STATE Buffer
DM74ALS125 Quad 3-STATE Buffer
November 1989 Revised February 2000
DM74ALS125 Quad 3-STATE Buffer
General Description
...
Description
DM74ALS125 Quad 3-STATE Buffer
November 1989 Revised February 2000
DM74ALS125 Quad 3-STATE Buffer
General Description
This device contains four independent gates each of which performs a non-inverting buffer function. The outputs have the 3-STATE feature. The 3-STATE circuitry contains a feature that maintains the buffer outputs in 3-STATE (high impedance state) during power supply ramp-up or rampdown. This eliminates bus glitching problems that arise during power-up and power-down. To minimize the possibility that two outputs will attempt to take a common bus to opposite logic levels, the disable time is shorter than the enable time of the outputs.
Features
s Advanced low power Schottky TTL process oxide-isolated ion-implanted s Functional and pin compatible with the 74LS counterpart s Switching response specified into 500Ω and 50 pF load s Switching response specifications guaranteed over full temperature and VCC supply range s PNP input design reduces input loading s Low level drive current: 74ALS = 24 mA
Ordering Code:
Order Number DM74ALS125M DM74ALS125N Package Number M14A N14A Package Description 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Logic Diagram
Functional Table
Y=A Input A L H X C L L H Output Y L H Hi-Z
H = HIGH Logic Level L =...
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