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DM7473 Datasheet

Part Number DM7473
Manufacturers Fairchild Semiconductor
Logo Fairchild Semiconductor
Description Dual Master-Slave J-K Flip-Flop
Datasheet DM7473 DatasheetDM7473 Datasheet (PDF)

DM7473 Dual Master-Slave J-K Flip-Flops with Clear and Complementary Outputs September 1986 Revised February 2000 DM7473 Dual Master-Slave J-K Flip-Flops with Clear and Complementary Outputs General Description This device contains two independent positive pulse triggered J-K flip-flops with complementary outputs. The J and K data is processed by the flip-flops after a complete clock pulse. While the clock is LOW the slave is isolated from the master. On the positive transition of the clock, t.

  DM7473   DM7473






Part Number DM7476
Manufacturers National Semiconductor
Logo National Semiconductor
Description Dual Master-Slave J-K Flip-Flops
Datasheet DM7473 DatasheetDM7476 Datasheet (PDF)

5476 DM5476 DM7476 Dual Master-Slave J-K Flip-Flops with Clear Preset and Complementary Outputs June 1989 5476 DM5476 DM7476 Dual Master-Slave J-K Flip-Flops with Clear Preset and Complementary Outputs General Description This device contains two independent positive pulse triggered J-K flip-flops with complementary outputs The J and K data is processed by the flip-flop after a complete clock pulse While the clock is low the slave is isolated from the master On the positive transition of the .

  DM7473   DM7473







Part Number DM7476
Manufacturers Fairchild Semiconductor
Logo Fairchild Semiconductor
Description Dual Master-Slave J-K Flip-Flop
Datasheet DM7473 DatasheetDM7476 Datasheet (PDF)

DM7476 Dual Master-Slave J-K Flip-Flops with Clear, Preset, and Complementary Outputs September 1986 Revised February 2000 DM7476 Dual Master-Slave J-K Flip-Flops with Clear, Preset, and Complementary Outputs General Description This device contains two independent positive pulse triggered J-K flip-flops with complementary outputs. The J and K data is processed by the flip-flop after a complete clock pulse. While the clock is LOW the slave is isolated from the master. On the positive transitio.

  DM7473   DM7473







Part Number DM7475
Manufacturers National Semiconductor
Logo National Semiconductor
Description Quad Latches
Datasheet DM7473 DatasheetDM7475 Datasheet (PDF)

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  DM7473   DM7473







Part Number DM7474N
Manufacturers Fairchild Semiconductor
Logo Fairchild Semiconductor
Description Dual Positive-Edge-Triggered D-Type Flip-Flop
Datasheet DM7473 DatasheetDM7474N Datasheet (PDF)

DM7474 Dual Positive-Edge-Triggered D-Type Flip-Flops with Preset, Clear and Complementary Outputs September 1986 Revised July 2001 DM7474 Dual Positive-Edge-Triggered D-Type Flip-Flops with Preset, Clear and Complementary Outputs General Description This device contains two independent positive-edge-triggered D-type flip-flops with complementary outputs. The information on the D input is accepted by the flip-flops on the positive going edge of the clock pulse. The triggering occurs at a volt.

  DM7473   DM7473







Part Number DM7474M
Manufacturers Fairchild Semiconductor
Logo Fairchild Semiconductor
Description Dual Positive-Edge-Triggered D-Type Flip-Flop
Datasheet DM7473 DatasheetDM7474M Datasheet (PDF)

DM7474 Dual Positive-Edge-Triggered D-Type Flip-Flops with Preset, Clear and Complementary Outputs September 1986 Revised July 2001 DM7474 Dual Positive-Edge-Triggered D-Type Flip-Flops with Preset, Clear and Complementary Outputs General Description This device contains two independent positive-edge-triggered D-type flip-flops with complementary outputs. The information on the D input is accepted by the flip-flops on the positive going edge of the clock pulse. The triggering occurs at a volt.

  DM7473   DM7473







Dual Master-Slave J-K Flip-Flop

DM7473 Dual Master-Slave J-K Flip-Flops with Clear and Complementary Outputs September 1986 Revised February 2000 DM7473 Dual Master-Slave J-K Flip-Flops with Clear and Complementary Outputs General Description This device contains two independent positive pulse triggered J-K flip-flops with complementary outputs. The J and K data is processed by the flip-flops after a complete clock pulse. While the clock is LOW the slave is isolated from the master. On the positive transition of the clock, the data from the J and K inputs is transferred to the master. While the clock is HIGH the J and K inputs are disabled. On the negative transition of the clock, the data from the master is transferred to the slave. The logic states of the J and K inputs must not be allowed to change while the clock is HIGH. Data transfers to the outputs on the falling edge of the clock pulse. A LOW logic level on the clear input will reset the outputs regardless of the logic states of the other inputs. Ordering Code: Order Number DM7473N Package Number N14A Package Description 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Connection Diagram Function Table Inputs CLR L H H H H CLK J X L H L H K X L L H H Q L Q0 H L Toggle Outputs Q H Q0 L H H = HIGH Logic Level L = LOW Logic Level X = Either LOW or HIGH Logic Level = Positive pulse data. the J and K inputs must be held constant while the clock is HIGH. Data is transferred to the outputs on the falling edge of the clock pulse. .


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