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DM54LS73A Datasheet

Part Number DM54LS73A
Manufacturers National Semiconductor
Logo National Semiconductor
Description Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops
Datasheet DM54LS73A DatasheetDM54LS73A Datasheet (PDF)

DM54LS73A DM74LS73A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Clear and Complementary Outputs June 1989 DM54LS73A DM74LS73A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Clear and Complementary Outputs General Description This device contains two independent negative-edge-triggered J-K flip-flops with complementary outputs The J and K data is processed by the flip-flops on the falling edge of the clock pulse The clock triggering occurs at a voltage level and.

  DM54LS73A   DM54LS73A






Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops

DM54LS73A DM74LS73A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Clear and Complementary Outputs June 1989 DM54LS73A DM74LS73A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops with Clear and Complementary Outputs General Description This device contains two independent negative-edge-triggered J-K flip-flops with complementary outputs The J and K data is processed by the flip-flops on the falling edge of the clock pulse The clock triggering occurs at a voltage level and is not directly related to the transition time of the negative going edge of the clock pulse The data on the J and K inputs is allowed to change while the clock is high or low without affecting the outputs as long as setup and hold times are not violated A low logic level on the clear input will reset the outputs regardless of the levels of the other inputs Connection Diagram Dual-In-Line Package www.DataSheet4U.com TL F 6372 – 1 Order Number DM54LS73AJ DM54LS73AW DM74LS73AM or DM74LS73AN See NS Package Number J14A M14A N14A or W14B Function Table Inputs CLR L H H H H H CLK X J X L H L H X K X L L H H X Q L Q0 H L Toggle Q0 Q0 Outputs Q H Q0 L H v v v v H H e High Logic Level L e Low Logic Level X e Either Low or High Logic Level v e Negative going edge of pulse Q0 e The output logic level before the indicated input conditions were established Toggle e Each output changes to the complement of its previous level on each falling edge of the clock pulse C1995 National Semiconduc.


2007-06-04 : 40N03P    1N4164A    1N415xA    1N416xA    1N417xA    1N418xA    1N419xA    1N416xB    1N417xB    1N440xB   


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