DL654

Core Logic '/[ $0,+*  PLFURQ &026 *DWH $UUD\ Description DL65x is a family of transparent, buffered D latches with active low gate transparency. SET is active low. Logic Symbol Truth Table DL65x DSQ G Q SN GN D Q QN L XXH L H H X NC NC HL L LH H L HH L NC = No Change HDL Syntax Verilog .................... DL65x inst_name (Q, QN, D, GN, SN); VHDL...................... inst_name: DL65x port map (Q, QN, D, GN, SN); Pin Loading Pin Name D GN SN DL651 1.0 1.0 1.0 Equivalent Loads DL652 DL654 1.0 1.0 1.0 1.0 1.0 1.0 DL656 1.0 1.0 1.0 Size And Power Characteristics Cell DL651 DL652 Equivalent Gates 6.0 7.0 Power Characteristicsa Static IDD (TJ = 85°C) (nA) EQLpd (Eq-load) TBD 12.6 TBD 15.7 DL654 DL656 10.0 12.0 TBD TBD 27.2 33.9 a. See page 2-15 for power equation. ® 3-110 Core Logic ® Propagation Delays (ns) Conditions: TJ = 25°C, VDD = 5.0V, Typical Process Number of Equivalent Loads 1 DL651 From: D To: Q tPLH tPHL From: D To: QN tPLH ...