CMOS Gate Array
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$0,+* PLFURQ &026 *DWH $UUD\
Description
DF40x is a family of static, master-slave, multiplexed scan D fl...
Description
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$0,+* PLFURQ &026 *DWH $UUD\
Description
DF40x is a family of static, master-slave, multiplexed scan D flip-flops. SET is asynchronous and active low. Outputs are buffered and change state on the rising edge of the clock.
Logic Symbol DF40x
DS C SD SE
Q Q
Truth Table C D SD SE SN Q QN ↑HX LHHL ↑LXLHLH ↑ XHHHH L ↑X LHHLH XXXXLHL L X X X H NC NC NC = No Change
Core Logic
HDL Syntax Verilog .................... DF40x inst_name (Q, QN, C, D, SD, SE, SN); VHDL...................... inst_name: DF40x port map (Q, QN, C, D, SD, SE, SN);
Pin Loading
Pin Name
C D SD SE SN
DF401 1.0 1.0 1.0 2.1 2.1
Equivalent Loads
DF402
DF404
1.0 1.0
1.0 1.0
1.0 1.0
2.1 2.2
2.1 3.1
DF406 1.0 1.0 1.0 2.2 3.1
Size And Power Characteristics
Power Characteristicsa
Cell Equivalent Gates
Static IDD (TJ = 85°C) (nA)
EQLpd (Eq-load)
DF401
11.0
TBD
22.8
DF402
12.0
TBD
26.1
DF404
15.0
TBD
37.3
DF406
18.0
TBD
44.2
3-79
Core Logic
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