DF231

') ® $0,+*  PLFURQ &026 *DWH $UUD\ Description DF231 is a static, master-slave, multiplexed scan D flip-flop. SET and RESET are asynchronous and active low. Output is unbuffered and changes state on the rising edge of the clock. Logic Symbol DF231 DS C SD SE R Q Truth Table C D RN ↑HH ↑LH ↑XH ↑XH XX L XXH XX L L XH NC = No Change SD SE SN Q X LHH XLHL HHHH L HH L XXHL XX LH X X L IL X X H NC IL = Illegal Condition Pin Loading Equivalent Load C 1.0 D 1.0 RN 2.1 SD 1.0 SE 2.1 SN 2.1 Core Logic Equivalent Gates ................... 12.0 HDL Syntax Verilog .................... DF231 inst_name (Q, C, D, RN, SD, SE, SN); VHDL...................... inst_name: DF231 port map (Q, C, D, RN, SD, SE, SN); Size And Power Characteristics Parameter Value Static IDD (TJ = 85°C) EQLpd See page 2-15 for power equation. TBD 22.7 Units nA Eq-load Propagation Delays Conditions: TJ = 25°C, VDD = 5.0V, Typical Process From Delay (ns) To Parameter 1 Number of Equivalent Lo...